1. Field of the Invention
The present invention relates to a technology for controlling a cache that includes ways including a plurality of blocks that store therein entry data, and more particularly, to a technology for controlling block degradation.
2. Description of the Related Art
Cache memories are low-capacity and high-speed memories that are widely used to solve problems caused by difference in performance between a processor such as a central processing unit (CPU) and a storage device such as a memory. The cache memory includes a plurality of ways arranged in parallel. Each of the ways includes a plurality of storage units called “block” as many as indices of the cache memory. A group of blocks in different ways having the same index (i.e., blocks within the same cache line) is usually accessed simultaneously.
Tag random access memories (tag RAMs) are used to store therein tags indicative of addresses where cache data, which is stored in the cache memory, is on a main memory actually. Such a tag RAM provides a list of addresses of the cache data for the CPU. The data structure of the tags stored in the tag RAM is same as the above-described data structure using ways and blocks.
Accesses to a specific block, which are the storage unit in the cache memory, may frequently fail due to a memory failure. If such access errors occur, it is necessary to set the specific block that causes the access errors to an unavailable state, i.e., to degrade the specific block, to avoid occurrence of a serious failure.
In one of degradation methods, if the failure occurs in the specific block, the whole way including the specific block is degraded. Although the block that causes the failure can be easily degraded by the degradation method mentioned earlier, all the blocks in the same way cannot be used, which results in decreasing performance of the cache memory. In contrast, Japanese Patent Application Laid-open No. S60-101656 and Japanese Patent Application Laid-open No. H2-302856 disclose technologies for degrading, if a failure has occurred in a specific block, the specific block only.
However, if the technologies disclosed in Japanese Patent Application Laid-open No. S60-101656 and Japanese Patent Application Laid-open No. H2-302856 are used, degradation data indicative of a degradation status is stored corresponding to each one of the failed blocks, which increases an amount of data in the circuit. To be specific, if there are many ways including many blocks, i.e., there are many blocks, a large amount of degradation data is required, as a result of which a larger part of storage circuit is occupied by the degradation data.
For this reason, there are needs for producing a cache controller that degrades not the whole way but the failed block by using a lower amount of the degradation data. Such problem commonly arises in a data processor including the cache memory.